Typically, a via is used to connect a lower metal interconnection to an upper metal interconnection in forming multi-layer metal interconnections.
FIGS. 1a and 1b are cross-sectional views illustrating a conventional method of forming a field programmable gate array (FPGA).
Referring to FIG. 1a, field oxide layers 12 are formed in a semiconductor substrate 11, and then a gate oxide layer 13, a gate electrode 14a and a spacer 14b are formed on the semiconductor substrate 11. A source/drain (not shown) is formed through ion implantation, and a silicide 15 is formed on the surface of the gate electrode 14a. Although not shown in FIG. 1a, the silicide 15 is also formed on the surface of the source/drain.
A pre metal dielectric (PMD) 16 is deposited on the obtained semiconductor substrate 11 and then a chemical mechanical polishing (CMP) process is performed.
The PMD 16 is then etched to form contact holes that open the surfaces of the gate electrodes 14a and the semiconductor substrate 11, and then the contact holes are buried with a metal material to form contacts 17. First metal interconnections M1 are formed which are connected to the contacts 17.
As shown in FIG. 1b, a first inter metal dielectric (IMD) 18a is deposited on the first metal interconnections M1 through a deposition process and is planarized through the CMP process.
First vias 19a connected to some of the first metal interconnections M1 are formed through a “Via1” patterning process. Further, second metal interconnections M2 connected to the first vias 19a are formed.
Then, a second IMD 18b, second vias 19b, and third metal interconnections M3 are sequentially formed, resulting in an FPGA.
However, a conventional FPGA process as shown in FIGS. 1a and 1b uses too many processes and masks, such as a metal interconnection mask and a via mask. This increases cost of manufacturing semiconductor devices.